1. Field of the Invention
The present invention relates to a semiconductor device having a bipolar transistor such as BiMOS (bipolar-Metal Oxide Semiconductor), and to a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a BiMOS has been known in which bipolar and MOS devices are formed on the same substrate so as to utilize advantages of both devices. An example of a circuit including this BiMOS is shown in FIG. 29, which is an equivalent circuit diagram illustrating an example of a circuit including a conventional BiNMOS.
Referring to FIG. 29, provided in the above-mentioned circuit including a BiNMOS are a p channel MOS transistor Q1, an n channel MOS transistor Q2, an npn bipolar transistor Q4, and an n channel MOS transistor Q3.
One impurity region of p channel MOS transistor Q1 is connected to a power supply Vcc. Gate electrode of this p channel MOS transistor Q1 is connected to an input terminal IN.
One impurity region of n channel MOS transistor Q2 is connected to the other impurity region of the p channel MOS transistor Q1. The other impurity region of this n channel MOS transistor Q2 is connected to the ground. Gate electrode of this n channel MOS transistor Q2 is also connected to the input terminal IN.
Collector region of the npn bipolar transistor Q4 is connected to the power supply Vcc. Base region of the npn bipolar transistor Q4 is connected to the other impurity region of the p channel MOS transistor Q1 and one impurity region of the n channel MOS transistor Q2. Emitter region of the npn bipolar transistor Q4 is connected to an external output terminal OUT.
One impurity region of the n channel MOS transistor Q3 is connected to the external output terminal OUT. The other impurity region of the n channel MOS transistor Q3 is connected to the ground. Gate electrode of the n channel MOS transistor Q3 is connected to the input terminal IN.
Operation of the circuit including the above-described BiNMOS is as follows. Example of High level potential being applied to the input terminal IN will be described first. When a High level potential is applied to the input terminal IN, the p channel MOS transistor Q1 will be turned off. The n channel MOS transistor Q2 will be turned on. This would turn npn bipolar transistor Q4 off, while causing the n channel MOS transistor Q3 to be turned on. Thus, the potential of the output terminal OUT is decreased and a Low level potential will be output.
The operation when Low level potential is applied to the input terminal IN is as follows. When a Low level potential is applied to the input terminal IN, p channel MOS transistor Q1 turns on, and n channel MOS transistor Q2 turns off. This would turn npn bipolar transistor Q4 on while causing n channel MOS transistor Q3 to be turned off. Accordingly, current flows through the npn bipolar transistor Q4 to the external output terminal OUT, thus increasing its potential. This means that a High level potential is output.
Referring to FIGS. 30 to 38, a cross sectional structure of the circuit shown in FIG. 29 will be described in detail. FIGS. 30 to 38 show cross sectional structure corresponding to portion 100 of FIG. 29.
Referring to FIG. 30, n channel MOS transistor Q3 and npn bipolar transistor Q4 are formed respectively on a main surface of a p type semiconductor substrate 101. N channel MOS transistor Q3 has n type impurity regions 109, 109 which are to be source/drain regions, and a gate electrode 102. Concentration of this n type impurity regions 109, 109 is about 10.sup.19 cm.sup.-3 to about 10.sup.20 cm.sup.-3. Npn bipolar transistor Q4 has an n type collector region 104, a p type base region 105, and an n type emitter region 106.
Beneath the collector region 104, an n type floating collector region 108 is formed, partially overlapping this collector region 104. Also, at collector region 104, an n type collector wall region 107 is formed under the region where a collector electrode is formed. The concentration of the collector wall region 107 is about 10.sup.19 cm.sup.-3 to about 10.sup.20 cm.sup.-3. This collector wall region 107 together with the floating collector region 108 serves to reduce the resistance of the current flowing through npn bipolar transistor Q4.
In an element isolation region at the main surface of p type semiconductor substrate 101, an isolation insulating film 110 is formed selectively. Also formed on the main surface of the p type semiconductor substrate 101 are gate insulating film 111 and interlayer insulating film 112. In interlayer insulating film 112, contact holes 128a, 128b, 128c, 128d and 128e are formed, at regions positioned above the impurity regions 109 which are to be source/drain regions of the n channel MOS transistor Q3, and above base region 105, emitter region 106, and collector wall region 107, respectively.
In these contact holes 128a to 128e, metal electrodes 113a, 113b, 113c, 113d, and 113e are formed, respectively. Material of this metal electrodes 113a to 113e may be aluminum (Al) or the like.
Method of manufacturing the BiNMOS shown in FIG. 30 will now be described. FIGS. 31 to 38 are cross sectional views illustrating the first to eighth steps in the manufacturing process of BiNMOS shown in FIG. 30.
Referring first to FIG. 31, resist is applied on the main surface of p type semiconductor substrate 101. Then, the resist is patterned by photolithography to form a resist pattern 115 exposing the region where a collector is to be formed. Using this resist pattern 115 as a mask, an n type impurity such as phosphorus (P) is implanted into the main surface of p type semiconductor substrate 101 thereby forming the collector region 104. Resist pattern 115 is then removed.
Referring now to FIG. 32, resist is applied on the main surface of p type semiconductor substrate 101. The resist is patterned by photolithography to form a resist pattern 116 partially exposing the surface of the collector region 104. Using this resist pattern 116 as a mask, the n type impurity such as phosphorus (P) is implanted into the main surface of p type semiconductor substrate 101 thereby forming the floating collector region 108.
Referring now to FIG. 33, after removing the above-mentioned resist pattern 116, isolation insulating film 110 is formed selectively on the predetermined regions of the main surface of p type semiconductor substrate 101, using LOCOS (Local Oxidation of Silicon) method. Gate oxide film 111 is formed.
Resist is then applied again on the p type semiconductor substrate 101, and is patterned by photolithography. This forms a resist pattern 117 on the main surface of p type semiconductor substrate 101, exposing the region where the collector wall region 107 is to be formed. Using this resist pattern 117 as a mask, the n type impurity such as phosphorus (P) is implanted into the main surface of p type semiconductor substrate 101 with a predetermined energy, thereby forming the collector wall region 107. Resist pattern 117 is then removed.
Referring now to FIG. 34, a polycrystalline silicon layer is deposited entirely on the main surface of p type semiconductor substrate 101 by, for example, CVD (Chemical Vapor Deposition). By patterning this polycrystalline silicon layer, gate electrode 102 of n channel MOS transistor Q3 is formed.
Referring now to FIG. 35, resist is applied again on the main surface of p type semiconductor substrate 101. The resist is patterned by photolithography to form a resist pattern 118 exposing the region where n channel transistor Q3 is to be formed.
Using this resist pattern 118 and gate electrode 102 as masks, an n type impurity such as arsenic (As) is implanted into the main surface of p type semiconductor substrate 101, thereby forming impurity regions 109, 109 which will be source/drain regions of n channel MOS transistor Q3. Resist pattern 118 is then removed.
Referring now to FIG. 36, resist is applied again on the main surface of p type semiconductor substrate 101. The resist is patterned by photolithography to form a resist pattern 119 on the main surface of p type semiconductor substrate 101, exposing gate oxide film 111 on the surface of base region 105. Using this resist pattern 119 as a mask, a p type impurity such as boron (B) is implanted into the main surface of p type semiconductor substrate 101, thereby forming base region 105. Resist pattern 119 is then removed.
Referring now to FIG. 37, resist is applied again on the main surface of p type semiconductor substrate 101. The resist is patterned by photolithography to form a resist pattern 120 on the main surface of p type semiconductor substrate 101, exposing gate oxide film 111 positioned above emitter region 106. Using this resist pattern 120 as a mask, the n type impurity such as arsenic (As) is implanted into the main surface of p type semiconductor substrate 101, thereby forming the emitter region 106. Resist pattern 120 is then removed.
Referring now to FIG. 38, interlayer insulating film 112 consisting of silicon oxide film and the like is formed entirely on the main surface of p type semiconductor substrate 101. Then, contact holes 128a, 128b, 128c, 128d, and 128e are formed at regions positioned above impurity regions 109 of the n channel MOS transistor Q3, base region 105, emitter region 106 and collector wall region 107, respectively, by photolithography and etching.
Referring now to FIG. 30, a metal layer such as aluminum (Al) is deposited in contact holes 128a, 128b, 128c, 128d, and 128e, and above interlayer insulating film 112. By patterning this metal layer to a predetermined shape, metal electrodes 113a, 113b, 113c, 113d, and 113e are formed, respectively. Through the process described above, the structure shown in FIG. 30 is obtained.
However, there has been the following problem in the BiNMOS manufacturing process described above. That is, the BiNMOS includes many impurity regions of different types of conductivity, such as the p type base region 105 and the n type collector region 104. Having many impurity regions of different conductivity types requires formation of many resist patterns 115, 116, 117, 118, 119, and 120 when those regions are formed, which function as mask layers. Conventionally, this has been generally considered inevitable in order to prevent bad influence on the performance of the device, which bad influence was caused by impurities with different types of conductivity being introduced to regions other than predetermined regions.
As a result, many processes of photolithography have been required in order to form many resist patterns as discussed above. The process of photolithography includes various steps such as resist application, mask alignment, exposure, development and inspection. The increased number of such processes which involves many steps inevitably leads to the problem of increased manufacturing costs.